All Mode Transmit, Receive and Digital Readout Adapter for the RA17.
By D. W. Knight.
Version: 1.00 (Unicode).

Part 3.

System Control Logic:
From the preceding design specifications, it emerges that there will be no need to alter the settings of any synthesisers on going from receive to transmit (and consequently no settling-time problems). T-R switching is therefore essentially a matter of activating the stages necessary to produce an RF output, and signalling the final amplifier to perform antenna switching and receiver muting functions. It also emerges that the modes: 'Aux.', 'FM', 'AM', 'Cent./Tune', and 'BFO/CW', all require the carrier generator to produce a channel centred (100KHz) output; and so (ignoring signal-path differences) can be treated as a single group from the system-control point of view. ('Aux.' mode belongs to the channel-centred-carrier group because, although the carrier frequency is irrelevant, the counter is required to display the channel centre frequency.)

Note that carrier synthesiser programming and frequency counting mode selection are linked functions, and will therefore share the same control logic.

When a converter is in use, it must request a counting scheme (N+3 or N-2) and send MHz data to an input port. When a converter requisitions the system, the internal 'N+3' synthesiser is disabled , but the interpolation TX output is available.

Frequency Counting Modes:
Recall that to obtain the operating frequency of a superhet from its VFO frequency requires a notional subtraction,
ie., f0 = fVFO - fIF.
In offset-counting, the subtraction is accomplished using modular arithmetic; by presetting the VFO counting register, so that its contents do not reach zero until a pre-determined number of pulses have been received. The offset-counting technique will be assumed here, with the additional complication that the counter must count downwards when the Wadley front-end or an 'N+3' type converter is in use, and upwards otherwise. The 'offset' is simply the number which must be loaded into the count register before counting commences. In the notation used here, an underscore character '_' is used to indicate the break-point between KHz and Hz, use of a decimal point being inappropriate because the offset is by definition a positive integer. A total of seven different offsets is needed to cover the required counting modes.

The full set of counting modes is as follows:

	Wadley (N+3)	LF (N-2)
Central Carrier	Offset=100_00 down-count VFO	Offset=900_00 up-count VFO
USB	Carrier=98.2KHz. Offset=098_20 down-count VFO	Carrier=101.8KHz Offset=898_20 up-count VFO
LSB	Carrier=101.8KHz Offset=101_80 down-count VFO	Carrier=98.2KHz Offset=901_80 up-count VFO
Variable CIO	Offset=000_00 up-count BFO down-count VFO	Offset=000_00 down-count BFO up-count VFO
External Inputs	Parallel MHz data input ignored. KHz overflow to MHz register Offset=000_00 up-count external input.
Read BFO	MHz readout blanked. BFO switched on. Offset=000_00 up-count BFO
Tube Cycle	Roll numbers for 10sec after switch-on.

Notes:
1) When the Wadley front-end, or a converter (other than an LF adapter), is in use, the counter accepts parallel BCD MHz data for transfer to the display. If the interpolation receiver is tuned outside its 1MHz range, the MHz readout is 'corrected', by incrementing or decrementing the MHz count by 1.
2) When the LF adapter is in use, the MHz display should read '00' or be blanked; unless the receiver is tuned above 1MHz, in which case an unblanked MHz display should read '01' (and the over-range warning should light).
3) When the counter is used with an external input, the KHz count should overflow into the MHz readout. The MHz count can also be made to overflow into an additional ½ or 1½-digits, to permit readout of frequencies above 100 or 1000MHz (logic speed permitting).
4) Tube cycling mode is only required if Nixies are used. All symbol cathodes need to be illuminated at least once in every 100 power-on hours, to prevent cathode poisoning; and the best way to do this is in the manner of a power-on reset. Counters displays can be made to cycle through all numbers by applying an input, setting the data latches transparent, and disabling the reset signal.

Digital and Analog Systems Interface:

It is highly desirable that any clocked-logic circuitry should be safely locked inside a Faraday cage; and that any communication with it should take place, as far as possible, via DC control signals (which can be heavily filtered if necessary). The standard procedure is to provide a set of negative logic control lines, which can be shorted to ground as required to activate the various operating modes.

Notes:
5) 'Channel centred carrier' is chosen as the default counter mode because this results in the simplest switch wiring.
6) The LF VFO and BFO signals are used by both digital and analog systems. A buffer is inserted between analog and digital take-off points to prevent creep-back of digital noise.

Digital Frequency Readout and System Logic:
KHz Readout:
The KHz counter offset program (for fixed-offset counting) is as follows:

Offset Mode	Decimal	BCD
Cent · N+3	100_00	0001 0000 0000_0000 0000
Cent · N-2	900_00	1001 0000 0000_0000 0000
USB · N+3	098_20	0000 1001 1000_0010 0000
USB · N-2	898_20	1000 1001 1000_0010 0000
LSB · N+3	101_80	0001 0000 0001_1000 0000
LSB · N-2	901_80	1001 0000 0001_1000 0000
None	000_00	0000 0000 0000_0000 0000

It should be immediately obvious, that out of 20 input lines, only 8 need to be programmed and the rest may be grounded. Furthermore, there are two groups of lines (4 for USB and 2 for LSB) which always change together, reducing the number of control inputs to 4 (ie., 'USB', 'LSB', 'Cent OR LSB', and 'fixed offset N-2'). A single OR gate can be used to resolve these into four orthogonal inputs which will be designated: 'usb', 'lsb', 'cent', and 'n-2'.

For variable offset counting, a pipelined architecture will be used. I.e., the CIO and the VFO will be counted simultaneously in separate registers; the CIO frequency being accumulated in a register called the 'offset register', and loaded into the count register prior to VFO sampling. This method avoids the reduction in data refresh rate which occurs when using variable-offset mode in the author's previous adapter. Fixed offset working is simply a matter of disabling counting in the offset register and parallel-loading the offset instead. Note from the earlier system mode table, that counting directions of the offset and count registers are always in opposition, which reduces the number of count-direction (up/down) control lines to one.

The offset register always obtains its counting input from the CIO. The count register must be set to sample the VFO, External Input, CIO, or tube-cycling clock, depending on the mode. The tube-cycling clock is chosen to be a 10KHz signal from the reference divider chain, this being sufficient to cause the KHz × 100 tube to cycle once in 10 sec. An alternative method for reading the CIO frequency would be to enable counting in the offset register and inhibit counting in the count register, but this precludes omitting the offset register (and linking across the IC patches) in the event that variable offset mode is not required.

Mode		Offset				Offset count enable	Count Dir	Counter Input
		usb	lsb	cent	n-2
Cent	N+3	0	0	1	0	0	D	VFO
	N-2	0	0	1	1	0	U	VFO
USB	N+3	1	0	0	0	0	D	VFO
	N-2	1	0	0	1	0	U	VFO
LSB	N+3	0	1	0	0	0	D	VFO
	N-2	0	1	0	1	0	U	VFO
Var	N+3	0	0	0	0	1	D	VFO
	N-2	0	0	0	0	1	U	VFO
Ext	X	0	0	0	0	0	U	Ext
BFO	X	0	0	0	0	0	U	CIO
Cyc	X	0	0	0	0	X	U	10KHz

X=don't care.

Project abandoned.

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References and Further Reading:
Racal Technical Manuals: RA17L, RA17C12, RA117, MA350, RA37A, RA137.
Radio Frequency Transistors, Norm Dye and Helge Granberg, 1993. ISBN 0-7506-9059-3
ARRL Handbook, 77th Edn. 1999. ISBN: 0-87259-183-2.
Please see also; other articles on the home page.

D.W.Knight. 07/2000.

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